1. Field of the Invention
The present invention relates to an A/D converter, and more particularly to a sweep function in the A/D converter having a plurality of input channels.
2. Description of Prior Art
FIG. 3 is a block diagram showing a configuration of a microcomputer. In the Figure, numeral 100 indicates a one-chip microcomputer configured with semiconductor integrated circuit, numeral 101 indicates a CPU, numeral 102 indicates a memory, numeral 103 indicates an A/D converter for converting an analog signal into a digital signal, and numeral 104 indicates a bus which connects those members to each other. The A/D converter 103 has functions to select a predetermined optional signal from among analog signals to be inputted from a plurality of A/D conversion input terminals 105 provided in the microcomputer 100, and to convert the analog signal into a digital signal. The A/D converter further has a sweep function for selecting automatically and repeatedly an input terminal in a predetermined range among the A/D conversion input terminals 105 by shifting succeedingly, so as to carry out an A/D conversion (this operating mode is called as "sweep mode").
FIG. 4 is a block diagram showing a conventional example of the A/D converter configured as the above description. In the Figure, numeral 1 represents an A/D converter in which, for example, A/D conversion input terminals of 8 channels from channel 0 through channel 7 are selected at switches S0 through S7, and a selected channel is to be connected to the A/D converter 1. A channel selector 3 decides which is to be selected from among the switches S0 through S7. A result converted at the A/D converter 1 is stored in a register corresponding to a converted channel of a converted result storing register 2, and is read out by a CPU or the like. The channel selector 3 determines which switches among the switches S0 through S7 is to be turned on with a value designated by each channel setting bit (3 bits in this example) in a channel setting register 4. A channel setting determining circuit 5 can detect which channels among the channels to be converted from analog to digital is being converted dependent on each bit output of the channel setting register 4. Particularly, when the circuit is used at the sweep mode and a channel being converted reaches a designated channel and when an A/D conversion completion signal 1a is inputted, a channel setting bit initialization signal 5a is generated and a channel setting bit in the channel setting register 4 is initialized. The channel setting register 4 functions as a binary counter at the sweep mode, and data can be set optionally with input setting data d0, d1, d2 and can designate optionally which channel is to be converted from analog signal to digital signal.
Next, the operation of the device shown in FIG. 4 will be explained.
In the sweep mode, channels in a predetermined range among the channels 0 to 7 of the A/D conversion input channel are converted sequentially and this operation is repeated. For example, if the channels 0 through 3 are set as in the sweep mode, A/D conversions of 4 channels 0 to 3 are repeated. Since the start channel is always channel 0, the channel 0 is designated at first by channel setting bit in the channel setting register 4, and the channel selector 3 makes the switch S0 turn on, so that an analog signal from the channel 0 is inputted into the A/D converter 1. The result converted at the A/D converter 1 is stored in a register corresponding to the channel 0 in the converted result storing register 2. When the storing is finished and the conversion is completed, a channel setting bit in the channel setting register 4 designates the channel 1, turning on the switch S1 by the channel selector 3, so that an analog signal from the channel 1 is converted into a digital signal and is stored in the converted result storing register 2. This operation is repeated, and when the conversion of the channel 3 is completed, the setting of the channel 3 is detected by the channel setting determining circuit 5 since the sweep mode for the channels 0 to 3 had been previously selected. When an A/D conversion completion signal 1a is inputted, a channel setting bit initialization signal 5a is generated and the channel setting bit in the channel setting register 4 is initialized so as to designate the channel 0. In this manner, channel selection returns from the channel 3 to the channel 0 so as to perform repeatedly the A/D conversion of the 4 channels from 0 to 3.
The conventional A/D converter having a sweeping function is constructed as the above-mentioned description. In this converter, when a channel which had not been selected for the sweep mode is to be converted during sweeping operation, it was necessary that the sweep mode is shifted to another mode so as to select a desired channel for A/D conversion. When the mode is returned to the sweep mode, the conversion always begins from the channel 0 in the sweep mode, and since the channels which had been converted before the shift of the mode are to be converted once again, the converted results obtained before the shift of the mode can not be utilized, thereby useless operations are inevitable during the conversion.